Renesas Electronics /R7FA6M4AF /CAN0 /BCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CCLKS 0 (000)TSEG20 (00)SJW0BRP0 (Others)TSEG1

TSEG2=000, SJW=00, TSEG1=Others, CCLKS=0

Description

Bit Configuration Register

Fields

CCLKS

CAN Clock Source Selection

0 (0): PCLKB (generated by the PLL clock)

1 (1): CANMCLK (generated by the main clock oscillator)

TSEG2

Time Segment 2 Control

0 (000): Setting prohibited

1 (001): 2 Tq

2 (010): 3 Tq

3 (011): 4 Tq

4 (100): 5 Tq

5 (101): 6 Tq

6 (110): 7 Tq

7 (111): 8 Tq

SJW

Synchronization Jump Width Control

0 (00): 1 Tq

1 (01): 2 Tq

2 (10): 3 Tq

3 (11): 4 Tq

BRP

Baud Rate Prescaler Select

TSEG1

Time Segment 1 Control

0 (Others): Setting prohibited

3 (0x3): 4 Tq

4 (0x4): 5 Tq

5 (0x5): 6 Tq

6 (0x6): 7 Tq

7 (0x7): 8 Tq

8 (0x8): 9 Tq

9 (0x9): 10 Tq

10 (0xA): 11 Tq

11 (0xB): 12 Tq

12 (0xC): 13 Tq

13 (0xD): 14 Tq

14 (0xE): 15 Tq

15 (0xF): 16 Tq

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